HT16528-003 Просмотр технического описания (PDF) - Holtek Semiconductor
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HT16528-003 Datasheet PDF : 40 Pages
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HT16528
Parallel Mode (i80)
RS
CS
W R ,R D
D B 0~D B 7
( W r ite )
tf
tR S 8
tf
tr
tR H 8
tC C L R , tC C L W
tC Y C 8
tC C H R , tC C H W
tD S 8
tD H 8
tA C C 8
tO H 8
D B 0~D B 7
(R e a d )
Note:
The input signal rising time and falling time (tf, tr) is specified at 15ns or less.
All timing is specified using 20% and 80% of VDD as the reference.
tCCLW and tCCLR are specified as the overlap between CS as L and WR and RD at the L level.
Timing Conditions 3 for Serial Mode
Symbol
Parameter
tCYK
Shift Clock Cycle
Test Conditions
VDD
Conditions
4.5V~5.5V
SCK
2.7V~4.5V
tWHK
High-level
Width
Shift
Clock
Pulse 4.5V~5.5V
2.7V~4.5V
SCK
tWLK
Low-level
Width
Shift
Clock
Pulse 4.5V~5.5V
2.7V~4.5V
SCK
tHSTBK Shift Clock Hold Time
4.5V~5.5V
STD¯ ® SCK¯
2.7V~4.5V
tDS
Data Setup Time
4.5V~5.5V
Data ® SCK
2.7V~4.5V
tDK
Data Hold Time
4.5V~5.5V
SCK ® Data
2.7V~4.5V
tDKSTB ST Hold Time
4.5V~5.5V
SCK ® ST
2.7V~4.5V
tWSTB
ST Pulse Width
4.5V~5.5V
¾
2.7V~4.5V
tWAIT
Wait Time
4.5V~5.5V
8th CLK ® 1st CLK¯
2.7V~4.5V
tODO
Output Data Delay Time
4.5V~5.5V
ST¯ ® Data
2.7V~4.5V
Min.
500
1000
200
300
200
300
100
150
100
150
100
150
500
750
500
750
1
1
¾
¾
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Ta=25°C
Max. Unit
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ms
¾
ms
150
ns
300
ns
Rev. 1.10
17
July 5, 2011
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