HFA3842IN Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

HFA3842IN

Wireless LAN Medium Access Controller

Intersil 

HFA3842

Power Sequencing

The HFA3842 provides a number of firmware controlled port

pins that are used for controlling the power sequencing and

other functions in the front end components of the PHY.

Packet transmission requires precise control of the radio.

Ideally, energy at the antenna ceases after the last symbol of

information has been transmitted. Additionally, the

transmit/receive switch must be controlled properly to protect

the receiver. It's also important to apply appropriate

modulation to the PA while it's active.

Signaling sequences for the beginning and end of normal

transmissions are illustrated in Figure 25. Table 10 lists

applicable delays.

A transmission begins with PE2 as shown in Figure 25. Next,

the transmit/receive switch is configured for transmission via

the differential pair TR_SW and TR_SW_BAR. This is

followed by TX_PE which activates the transmit state

machine in the BBP. Lastly, PA_PE activates the PA. Delays

for these signals related to the initiation of transmission are

referenced to PE2.

Immediately after the final data bit has been clocked out of

the HFA3842, TX_PE is de-asserted. The HFA3842 then

waits for TXRDY to go inactive, signaling that the BBP has

modulated the final information-rich symbol. It then

immediately de-asserts PA_PE followed by placing the

transmit/receive switch in the receive position and ending

with PE2 going high. Delays for these signals related to the

termination of transmission are referenced to the rising edge

of PE2.

TABLE 10. TRANSMIT CONTROL TIMING SPECIFICATIONS

PARAMETER SYMBOL DELAY TOLERANCE UNITS

PE2 to TR Switch

tD1

2

PE2 to PA_PE

tD3

3

±0.1

µs

±0.1

µs

PA_PE to PE2

tD4

3

±0.1

µs

TR Switch to PE2

tD5

2

±0.1

µs

PE1 and PE2 encoding details are found in Table 11.

Note that during normal receive and transmit operation that

PE1 is static and PE2 toggles for receive and transmit

PE1

PE2

TR_SW

TR_SW_BAR

tD1

tD5

TX_PE

TX_RDY

PA_PE

tD3

tD4

FIGURE 25. TRANSMIT CONTROL SIGNAL SEQUENCING

.

TABLE 11. POWER ENABLE STATES

PE1

PE2

PLL_PE

Power Down State

0

0

1

Receive State

1

1

1

Transmit State

1

0

1

PLL Active State

0

1

1

PLL Disable State

X

X

0

TABLE 11. POWER ENABLE STATES

PE1

PE2

PLL_PE

NOTE:

22. PLL_PE is controlled via the serial interface, and can be used to

disable the internal synthesizer, the actual synthesizer control is

an AND function of PLL_PE, and a result of the OR function of

PE1 and PE2. PE1 and PE2 will directly control the power

enable functionality of the LO buffer(s)/phase shifter.

23

Share Link: