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HFA3842IN96

Wireless LAN Medium Access Controller

Intersil 

HFA3842

RAM, and then branches to begin execution from RAM. This

allows low cost, slow Flash devices to hold an entire code

image, which can be executed much faster from RAM. If code

is not placed in an external non-volatile memory as described

here, it must be transferred to the RAM via the Host Interface.

Slow memories are not dynamically sensed. Following reset,

the instruction clock operates with a slower cycle while the

Flash is copied to RAM. Once code has been copied from

Flash to RAM, execution transfers to RAM and the clock is

raised to the normal operating frequency.

As mentioned above, it is feasible to operate without a code

image in a non-volatile memory. In such a system, the

firmware must be downloaded to RAM through the host

interface before operation can commence.

The external SRAM memory must be organized in a 16-bit

width to provide adequate performance to implement the

802.11 protocol at 11Mb/s rates. Systems designed for lower

performance applications may be able to use 8-bit wide

memory.

The minimum external memory is 128Kbytes of SRAM,

organized 8 or 16 bits wide. Typical applications, including

802.11 station designs, use 256Kbytes organized 128K x 16.

An access point application could make use of the full address

space of the device with 4Mbytes organized a 2M x 16.

The HFA3842 supports 8 or 16 bit code space, and 8 or 16-bit

data space. Code space is typically populated with the less

expensive Flash memory available, usually an 8-bit device.

Data space is usually populated with high-speed RAMs

configured as a 16-bit space. This mixing of 8/16 bit spaces is

fully supported, and may be done in any combination desired

for code and data space.

The HFA3842 supports direct control of single chip 16-bit

wide SRAMs with high/low byte enables, as well as direct

control of a 16-bit space constructed from 8-bit wide SRAMs.

The type of memory configuration is specified via the

appropriate MD pin, sensed when the HFA3842 is reset.

HFA3842 pin MUBE-/MA0/MWEH- functions as Address 0

for 8-bit access, (such as Flash) as MWEH (High Byte Write

Enable) when two x8 memories are configured as a single

x16 space, and as the upper Byte Enable when a single x16

memory is used. No external logic is required to generate

the required signals for both types of memory configurations,

even when both exist together; all that is required is for the

HFA3842 code to configure the HFA3842 memory controller

to generate the proper signals for the particular address

space being accessed.

For 8-bit spaces, the HFA3842 dynamically configures pin

MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB.

MWEL-/MWE- is the only write control, and MOE- is the read

output enable.

For 16-bit spaces constructed from 8-bit memories, the

HFA3842 dynamically configures pin MUBE-/MA0/MWEH-

cycle-by-cycle as the high byte write enable, MWEL- as the low

write enable signal, and MOE- as the read output enable.

For 16-bit spaces constructed from single-chip x16 memories

(such as SRAMs), the HFA3842 dynamically configures pin

MUBE_/MA0/MWEH- cycle-by-cycle as the upper byte enable.

Pin MLBE- is connected as the low byte enable, MWEL-/MWE-

is the write control, and MOE- is the read output enable.

These memory implementations require no external logic. The

memory spaces may each be constructed from any type of

memory desired. The only restriction is that a single memory

space must be constructed from the same type of memory; for

example, data space may not use both x8 and x16 memories, it

must be all x8, or all x16. This restriction does not apply across

memory spaces; e.g., code space may use a x8 memory and

data space a single x16 memory, or code space two x8

memories and data space a single x8 memory.

Contact the factory for additional information in regards to

HFA3842 to PRISM II MAC-less Connections.

Serial EEPROM Interface

The HFA3842 contains a small on-chip ROM Firmware which

was added to allow the CIS or CIS plus firmware image to be

transferred from an off-chip serial non-volatile memory device

to RAM after a system Reset. This allows a system

configuration without a parallel Flash Device. The operating

frequency of the serial port is 400kHz with a voltage of 3.3V.

Refer to Figure 14 for additional details on configuring the serial

memory of the HFA3842. The Power On Reset Configuration

section in this data sheet provides additional details on memory

selection and control after a Reset condition.

Host Interface

PC Card Physical Interface

The Host interface is compatible to the PC Card 95 Standard

(PCMCIA v2.1). The HFA3842 Host Interface pins connect

directly to the correspondingly named pins on the PC Card

connector with no external components (other than

resistors) required. The HFA3842 operates as an I/O card

using less than 64 octet locations. Reads and writes to

internal registers and buffer memory are performed by I/O

accesses. Attribute memory (256 octets) is provided for the

CIS table which is located in external memory. Common

memory is not used.

The following describes specific features of various pins:

HA[9:0]

Decoding of the system address space is performed by the

HCEx-. During I/O accesses HA[5:0] decode the register.

HA[9:6] are ignored when the internal HAMASK register is

set to the defaults used by the standard firmware. During

attribute memory accesses HA[9:1] are used.

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