HDMP-1687 Просмотр технического описания (PDF) - HP => Agilent Technologies

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HDMP-1687

Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel

HP => Agilent Technologies 

TRx I/O Definition

Name

Type

SI [0:3]+

SI [0:3]–

HS_IN

SO [0:3]+

SO [0:3]–

HS_ OUT

SYNC

I-TTL

SYN [0:3]

N/C

LOOP

O-TTL

I-TTL

RCM0

I-TTL

RC [0:3] [0:1] O-TTL

RFCT

I-TTL

RX [0:3] [0]

RX [0:3] [1]

RX [0:3] [2]

RX [0:3] [3]

RX [0:3] [4]

RX [0:3] [5]

RX [0:3] [6]

RX [0:3] [7]

RX [0:3] [8]

RX [0:3] [9]

CAP0

CAP1

O-TTL

C

Signal

Serial Data Inputs: High-speed inputs. Serial data is accepted from the SI [0:3]±

inputs when LOOP is low.

Serial Data Outputs: High speed outputs. These lines are active when LOOP is

set low. When LOOP is set high, these outputs are held static at logic 1.

Enable Byte Sync Input: When high, turns on the internal byte sync functions to

allow clock synchronization to a comma character of positive disparity (0011111XXX).

When the line is low, the function is disabled and will not reset registers and clocks,

or strobe the SYN [0:3] lines.

Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma

character of positive disparity (0011111XXX) when SYNC is enabled.

These pins need to be left open. Do not apply voltage on this pin.

Loopback Enable Input: When set high, the high speed serial signal is internally

wrapped from the transmitter’s serial loopback outputs back to the receiver‘s

loopback inputs. Also when in loopback mode, the SO [0:3]± outputs are held static

at logic 1. When set low, SO [0:3]± outputs and SI [0:3]± inputs are active.

Receivers Clocking Mode Definition Pins: These pins define how received

parallel data are driven as follows:

RCM0 Receive Clock Mode

0

half speed dual clocks

1

full speed single clocks

Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks

RC [0:3] [1]. Alternatively, they may drive half speed clocks RC [0:3] [0:1]. See RCM0

definition.

Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host

system. The transmitter sections accept this signal as the frequency reference clock.

It is multiplied by 10 to generate the serial bit clock and other internal clocks. The

transmit sections use this clock as the transmit byte clock for transmitting parallel

data at TX [0:3] [0:9].

Data Outputs: Four 10 bit data bytes. RX [0:3] [0] are the first bits received.

Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected

across the CAP0 and CAP1 pins. (typical value = 0.1µF).

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