H8/3004 Просмотр технического описания (PDF) - Renesas Electronics

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производитель

H8/3004

Microcomputer

Renesas Electronics 

1.2 Block Diagram

Figure 1-1 shows an internal block diagram.

MD1

MD0

EXTAL

XTAL

ø

STBY

RES

RESO

NMI

AS

RD

WR

P60/WAIT

Clock

osc.

Data bus

Address bus

Data bus (upper)

Data bus (lower)

H8/300H CPU

Interrupt controller

Bus controller

RAM*

Wait-state controller

Watchdog timer

Serial communication

interface (SCI) × 1 channel

16 bit

integrated timer unit

(ITU)

A/D converter

Port B

Port A

Port 7

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

P83/IRQ3

P82/IRQ2

P81/IRQ1

P80/IRQ0

P94/SCK/IRQ4

P92/RxD

P90/TxD

Note: * 2 kbytes in the H8/3004, 4 kbytes in the H8/3005.

Figure 1-1 Block Diagram

4

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