HD404448 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD404448

Four timer/counters

Hitachi -> Renesas Electronics 

HD404449 Series

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the

interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to

that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in

figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The

IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

during the second and third cycles, and the program jumps to the vector address to execute the instruction

in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the

interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET, STOPC*

—

$0000

INT0

1

INT1

2

Timer A

3

$0002

$0004

$0006

Timer B, INT2

4

Timer C, INT3

5

Timer D, A/D

6

$0008

$000A

$000C

Serial 1, Serial 2

7

$000E

Note: * The STOPC interrupt request is valid only in stop mode

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