HCF40105B(2002) Просмотр технического описания (PDF) - STMicroelectronics

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производитель

HCF40105B
(Rev.:2002)

FIFO REGISTER

STMicroelectronics 

HCF40105B

FIFO REGISTER

s INDEPENDENT ASYNCHRONOUS INPUTS

AND OUTPUTS

s 3-STATE OUTPUTS

s EXPANDABLE IN EITHER DIRECTION

s STATUS INDICATORS ON INPUT AND

OUTPUT

s RESET CAPABILITY

s STANDARDIZED, SYMMETRICAL OUTPUT

CHARACTERISTICS

s QUIESCENT CURRENT SPECIF. UP TO 20V

s 5V, 10V AND 15V PARAMETRIC RATINGS

s INPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C

s 100% TESTED FOR QUIESCENT CURRENT

s MEETS ALL REQUIREMENTS OF JEDEC

JESD13B " STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DESCRIPTION

HCF40105B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP packages.

HCF40105B is a low power first-in-first-out (FIFO)

"elastic" storage register that can store 164-bit

words. It is capable of handling input and output

data at different shifting rates. This feature makes

it particularly useful as a buffer between

asynchronous systems. Each word position in the

register is clocked by a control flip-flop, which

stores a marker bit. "1" signifies that the position’s

data is filled and "0" denotes a vacancy in that

PIN CONNECTION

DIP

ORDER CODES

PACKAGE

TUBE

DIP

HCF40105BEY

T&R

position. The control flip-flop detects the state of

the preceding flip-flop and communicates its own

status to the succeeding flip-flop. When a control

flip flop is in the "0" state and sees a "1" in the

preceding flip-flop, it generates a clock pulse that

transfers data from the preceding four data

latches into its own four data latches and resets

the preceding flip-flop to "0". The first and last

control flip-flops have buffered outputs. Since all

empty locations "bubble" automatically to the input

end, and all valid data ripples through to the output

end, the status of the first control flip-flop

(DATA-IN READY) indicates if the FIFO is full, and

the status of the last flip-flop (DATA-OUT READY)

indicates if the FIFO contains data. As the earliest

data is removed from the bottom of the data stack

(the output and), all data entered later will

automatically propagate (ripple) toward the

output.

October 2002

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