GS1561(2007) Просмотр технического описания (PDF) - Gennum -> Semtech

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Компоненты Описание

производитель

GS1561
(Rev.:2007)

HD-LINX® II Dual-Rate Deserializer

Gennum -> Semtech 

Contents

GS1560A/GS1561 Data Sheet

Key Features .................................................................................................................1

Applications ...................................................................................................................1

Description ....................................................................................................................1

Functional Block Diagrams ...........................................................................................2

1. Pin Out .....................................................................................................................6

1.1 Pin Assignment GS1560A ..............................................................................6

1.2 Pin Assignment GS1561.................................................................................7

1.3 Pin Descriptions ..............................................................................................8

2. Electrical Characteristics ........................................................................................19

2.1 Absolute Maximum Ratings ..........................................................................19

2.2 DC Electrical Characteristics ........................................................................19

2.3 AC Electrical Characteristics.........................................................................21

2.4 Solder Reflow Profiles...................................................................................24

2.5 Input/Output Circuits .....................................................................................25

2.6 Host Interface Map........................................................................................27

2.6.1 Host Interface Map (R/W Configurable Registers) .............................28

2.6.2 Host Interface Map (Read Only Registers) .........................................29

3. Detailed Description ...............................................................................................30

3.1 Functional Overview .....................................................................................30

3.2 Serial Digital Input .........................................................................................31

3.2.1 Input Signal Selection .........................................................................31

3.2.2 Carrier Detect Input ............................................................................31

3.2.3 Single Input Configuration ..................................................................31

3.3 Serial Digital Reclocker .................................................................................32

3.3.1 External VCO......................................................................................32

3.3.2 Loop Bandwidth ..................................................................................32

3.4 Serial Digital Loop-Through Output (GS1560A only) ....................................33

3.4.1 Output Swing ......................................................................................33

3.4.2 Reclocker Bypass Control ..................................................................34

3.4.3 Serial Digital Output Mute...................................................................34

3.5 Serial-To-Parallel Conversion .......................................................................35

3.6 Modes Of Operation......................................................................................35

3.6.1 Lock Detect.........................................................................................35

3.6.2 Master Mode.......................................................................................36

3.6.3 Slave Mode.........................................................................................37

3.7 SMPTE Functionality ....................................................................................38

3.7.1 SMPTE Descrambling and Word Alignment .......................................38

3.7.2 Internal Flywheel.................................................................................38

3.7.3 Switch Line Lock Handling..................................................................39

3.7.4 HVF Timing Signal Generation ...........................................................43

27360 - 10 January 2007

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