GAL16V8 Просмотр технического описания (PDF) - Lattice Semiconductor

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GAL16V8

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

fmax Descriptions

CLK

Specifications GAL16V8

LOGIC

ARRAY

REGISTER

tsu

tco

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured

tsu and tco.

CLK

LOGIC

ARRAY

CLK

REGISTER

t cf

t pd

LOGIC

ARRAY

REGISTER

tsu + th

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

Switching Test Conditions

Input Pulse Levels

Input Rise

and Fall Times

GAL16V8D-10

(and slower)

GAL16V8D-3/-5/-7

GND to 3.0V

2 – 3ns 10% – 90%

1.5ns 10% – 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

3-state levels are measured 0.5V from

steady-state active level.

1.5V

1.5V

See figure at right

Table 2-0003/16V8

GAL16V8D (except -3) Output Load Conditions (see figure

above)

Test Condition

A

B Active High

Active Low

C Active High

Active Low

R1

200Ω

∞

200Ω

∞

200Ω

R2

390Ω

390Ω

390Ω

390Ω

390Ω

CL

50pF

50pF

50pF

5pF

5pF

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The

value of tcf is used primarily when calculating the delay from

clocking a register to a combinatorial output (through registered

feedback), as shown above. For example, the timing from clock

to a combinatorial output is equal to tcf + tpd.

+5V

R1

FROM OUTPUT (O/Q)

UNDER TEST

R2

TEST POINT

C L*

*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

14

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