FSA1259 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FSA1259 Datasheet PDF : 11 Pages
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Test Diagrams
VCC
VB 1B or 2B
A
S
GND
VOUT
RL
CL
50 35pF
Control
VCC
Input
0V
50%
tR = tF = 2.5ns
Switch
Output
VOUT
0V
0.9 x VOUT
tON
tOFF
0.9 x VOUT
CL includes fixture and stray capacitance.
Logic input waveforms inverted for switches
that have the opposite logic sense.
Figure 11. Turn On / Off Timing
VCC 10nF
0 or VCC
50
S
VCC
A
1B
2B
GND
VIN
VOUT
Network
Analyzer
50
50
MEAS
50
REF
50
OFF
ISOLATION
=
20log
VOUT
VIN
ON-LOSS
=
20log
VOUT
VIN
CROSSTALK
=
20log
VOUT
VIN
Figure 12. Off Isolation and Crosstalk
VGEN
RGEN
1B or 2B
GND
VCC
A
S
Control
Input
VOUT
CL
VOUT
In
Off
In Off
ΔVOUT
On
Off
On
Off
Q = (ΔVOUT) • (CL)
Figure 13. Charge Injection
© 2007 Fairchild Semiconductor Corporation
FSA1259 / FSA1259A Rev. 1.0.6
8
www.fairchildsemi.com
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