EX128-FCS128 Просмотр технического описания (PDF) - Actel Corporation
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EX128-FCS128 Datasheet PDF : 36 Pages
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eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.3V, TJ = 70°C)
‘–P’ Speed
‘Std’ Speed
Parameter Description
2.5V LVTTL Output Module Timing1 (VCCI = 2.3V)
tDLH
Data-to-Pad LOW to HIGH
tDHL
Data-to-Pad HIGH to LOW
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
tENZL
Enable-to-Pad, Z to L
tENZLS
Enable-to-Pad Z to L—Low Slew
tENZH
Enable-to-Pad, Z to H
tENLZ
Enable-to-Pad, L to Z
tENHZ
Enable-to-Pad, H to Z
dTLH
Delta Delay vs. Load LOW to HIGH
dTHL
Delta Delay vs. Load HIGH to LOW
dTHLS
Delta Delay vs. Load HIGH to LOW—Low
Slew
3.3V LVTTL Output Module Timing1 (VCCI = 3.0V)
tDLH
Data-to-Pad LOW to HIGH
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
dTLH
dTHL
Delta Delay vs. Load LOW to HIGH
Delta Delay vs. Load HIGH to LOW
dTHLS
Delta Delay vs. Load HIGH to LOW—Low
Slew
5.0V TTL Output Module Timing1 (VCCI = 4.75V)
tDLH
tDHL
tDHLS
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
tENZL
tENZLS
Enable-to-Pad, Z to L
Enable-to-Pad Z to L—Low Slew
tENZH
tENLZ
Note:
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
1. Delays based on 35 pF loading.
Min.
Max.
3.3
3.5
11.6
2.5
11.8
3.4
2.1
2.4
0.034
0.016
0.05
2.8
2.7
9.7
2.2
9.7
2.8
2.8
2.6
0.02
0.016
0.05
2.0
2.6
6.8
1.9
6.8
2.1
3.3
Min.
Max.
4.7
5.0
16.6
3.6
16.9
4.9
3.0
5.67
0.046
0.022
0.072
4.0
3.9
13.9
3.2
13.9
4.0
4.0
3.8
0.03
0.022
0.072
2.9
3.7
9.7
2.7
9.8
3.0
4.8
‘–F’ Speed
Min. Max.
6.6
7.0
23.2
5.1
23.7
6.9
4.2
7.94
0.066
0.05
0.1
5.6
5.4
19.5
4.4
19.6
5.6
5.6
5.3
0.046
0.05
0.1
4.0
5.2
13.6
3.8
13.7
4.1
6.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
v3.0
19
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