MAX7000B Просмотр технического описания (PDF) - Altera Corporation

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производитель

MAX7000B

Programmable Logic Device

Altera Corporation 

MAX 7000B Programmable Logic Device Data Sheet

Figure 8. MAX 7000B JTAG Waveforms

TMS

TDI

TCK

TDO

Signal

to Be

Captured

Signal

to Be

Driven

t JCP

t JCH

t JCL

t JPSU

tJPZX

tJSSU

tJPCO

tJSH

tJSZX

tJSCO

t JPH

t JPXZ

tJSXZ

Table 9 shows the JTAG timing parameters and values for MAX 7000B

devices.

Table 9. JTAG Timing Parameters & Values for MAX 7000B Devices

Note (1)

Symbol

Parameter

tJCP

tJCH

tJCL

tJPSU

tJPH

tJPCO

tJPZX

tJPXZ

tJSSU

tJSH

tJSCO

tJSZX

tJSXZ

TCK clock period

TCK clock high time

TCK clock low time

JTAG port setup time

JTAG port hold time

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

Update register clock to output

Update register high impedance to valid output

Update register valid output to high impedance

Note:

(1) Timing parameters in this table apply to all VCCIO levels.

Min Max Unit

100

ns

50

ns

50

ns

20

ns

45

ns

25 ns

25 ns

25 ns

20

ns

45

ns

25 ns

25 ns

25 ns

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