EM78P159N
8-Bit Microcontrollerwith OTP ROM
The Data Memory Configuration is as follows:
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
︰
3F
R PAGE Registers
R0
R1
R2
R3
R4
R5
R6
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
RD
RE
RF
(IAR)
(TCC)
(PC)
(Status)
(RSR)
(Port5)
(Port6)
(Only for simulator)
(Wake up control)
(Interrupt Status)
General Registers
Reserve
CONT
Reserve
Reserve
Reserve
IOC5
IOC6
Reserve
Reserve
Reserve
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
IOC PAGE Registers
(Control Register)
(I/O Port Control Register)
(I/O Port Control Register)
(Prescaler Control Register)
(Pull-down Register)
(Open-drain Control)
(Pull-high Control Register)
(WDT Control Register)
(Interrupt Mask Register)
4.1.4 R3 (Status Register)
Bit 7
GP2
Bit 6
GP1
Bit 5
GP0
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
Bit 0 (C) Carry flag
Bit 1 (DC) Auxiliary carry flag
Bit 2 (Z)
Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 3 (P)
Power down bit.
Set to “1” during power on or by a "WDTC" command; and reset to “0” by a
"SLEP" command.
Bit 4 (T)
Time-out bit.
Set to “1” with the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bit 5 ~7 (GP0 ~ 2) General-purpose read/write bits.
8•
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)