EM78P153S
OTP ROM
PCRD
Q
P
R
D
_
Q
CLK
C
L
PCWR
PORT
Q
P
R
D
IOD
_
CLK
C
QL
PDWR
0
M
U
1
X
PDRD
*Pull-down is not shown in the figure.
Fig. 6 The circuit of I/O port and I/O control register for Port 5
PCRD
PORT
B it 6 of IO C E
D
P
R
Q
CLK _
C
L
Q
Q
P
R
D
_ CLK
QC
L
PCW R
0
M
1U
X
Q
P
R
D
_ CLK
QC
L
PDW R
PDRD
IO D
T10
D
P
R
Q
CLK _
C
L
Q
*Pull-high (down), Open-drain are not shown in the figure.
Fig. 7 The circuit of I/O port and I/O control register for P60(/INT)
This specification is subject to change without prior notice.
17
4. 1.2004 (V1.4)