Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Capacitance Derating
CLKO
(output)
DR
(input)
DSO
(output)
T0, T2 T1, T3
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30
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Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing
Capacitance Derating
The DSP56156 External Bus Timing Specifications are designed and tested at the maximum ca-
pacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the Exter-
nal Bus pins (A0-A15, D0-D15, PS/DS, RD, BS, WR, R/W) derates linearly at 1 ns per 12 pF of
additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns
per 5 pF of additional capacitance from 50 pF to 250 pF of loading.
When an internal memory access follows an external memory access, the PS/DS, R/W, RD
and WR strobes remain deasserted and A0-A15 do not change from their previous state.
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DSP56156 Data Sheet
MOTOROLA
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