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ABRIDGED DATA SHEET

DS2465

DeepCover Secure Authenticator with

SHA-256 Coprocessor and 1-Wire Master Function

1-Wire Master Status Register (61h)

The 1-Wire Master Status register is the general means for the DS2465 to report bit-type data from the 1-Wire side,

1-Wire busy status, and its own reset status to the host processor (Table 1). All 1-Wire communication commands and

the 1-Wire Master Reset command position the read pointer at the Status register for the host processor to read with

minimal protocol overhead. Status information is updated during the execution of certain commands only. Details are

given in the description of the various status bits that follow.

Table 1. 1-Wire Master Status Bit Assignment

BIT 7

DIR

BIT 6

TSB

BIT 5

SBR

BIT 4

RST

BIT 3

LL

BIT 2

SD

BIT 1

PPD

BIT 0

1WB

Bit 7: Branch Direction Taken (DIR). Whenever a 1-Wire Triplet command is executed, this bit reports to the host

processor the search direction that was chosen by the third bit of the triplet. The power-on default of DIR is 0. This bit is

updated only with a 1-Wire Triplet command and has no function with other commands. For additional information, see

the description of the 1-Wire Triplet command and Application Note 187: 1-Wire Search Algorithm.

Bit 6: Triplet Second Bit (TSB). The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the

second bit of a 1-Wire Triplet command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet

command and has no function with other commands.

Bit 5: Single Bit Result (SBR). The SBR bit reports the logic state of the active 1-Wire line sampled at tMSR of a 1-Wire

Single Bit command or the first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single

Bit command sends a 0 bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending

on the response of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends

a 1 bit.

Bit 4: Device Reset (RST). If the RST bit is 1, the DS2465 has performed an internal reset cycle, either caused by a

power-on reset, a low pulse at SLPZ, or from executing the Device Reset command. The RST bit is cleared automatically

when the 1-Wire Master Configuration register is updated by the host processor.

Bit 3: Logic Level (LL). The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire commu-

nication. The 1-Wire line is sampled for this purpose every time the 1-Wire Master Status register is read. The sampling

and updating of the LL bit takes place when the host processor has addressed the DS2465 in read mode (during the

acknowledge cycle), provided that the read pointer is positioned at the 1-Wire Master Status register.

Bit 2: Short Detected (SD). The SD bit is updated with every 1-Wire Reset command. If the DS2465 detects a logic 0

on the 1-Wire line at tSI during the presence-detect cycle, the SD bit is set to 1. This bit returns to its default 0 with a

subsequent 1-Wire Reset command provided that the short has been removed.

Bit 1: Presence-Pulse Detect (PPD). The PPD bit is updated with every 1-Wire Reset command. If the DS2465 detects

a presence pulse from a 1-Wire device at tMSP during the presence-detect cycle, the PPD bit is set to 1. This bit returns

to its default 0 if there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command.

Bit 0: 1-Wire Busy (1WB). The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire

communication 1WB is 1; once the command is completed, 1WB returns to its default 0. Details on when 1WB changes

state and for how long it remains at 1 are found in the Function Commands section.

1-Wire Read Data Register (62h)

When the DS2465 completes a 1-Wire Read Byte command, it puts the data read from the 1-Wire slave into the 1-Wire

Read Data register. While the command is being executed, the I2C host checks the 1WB bit in the 1-Wire Master Status

register. When the 1-Wire line is no longer busy, the I2C host performs a dummy write to address 62h and then accesses

the DS2465 in read mode to read the data byte.

Maxim Integrated

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