DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

Figure 36-12. Transmit-Side Timing, Elastic Store Enabled

tR

TSYSCLK

TSER

TCHCLK

TCHBLK

TSSYNC

tF

t SU

t D3

t HD

t D3

t SU

tHD

tSP

tSL tSH

Note 1: TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.

Note 2: TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled.

Figure 36-13. Transmit Line Interface Timing

TCLKO

TPOSO, TNEGO

tR

TCLKI

TPOSI, TNEGI

t DD

tF

tLP

t LL

tLH

t SU

t HD

DS2156

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