DS21552L Просмотр технического описания (PDF) - Maxim Integrated

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DS21552L

T1 Single-Chip Transceivers

Maxim Integrated 

4.1.2 RECEIVE SIDE PINS (cont.)

Signal Name:

RFSYNC

Signal Description:

Receive Frame Sync

Signal Type:

Output

An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.

DS21352/DS21552

Signal Name:

RMSYNC

Signal Description:

Receive Multiframe Sync

Signal Type:

Output

Only used when the receive side elastic store is enabled. An extracted pulse, one RSYSCLK wide, is output at this pin which

identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe boundaries

associated with RCLK.

Signal Name:

RDATA

Signal Description:

Receive Data

Signal Type:

Output

Updated on the rising edge of RCLK with the data out of the receive side framer.

Signal Name:

RSYSCLK

Signal Description:

Receive System Clock

Signal Type:

Input

1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the receive side elastic store function is enabled.

Should be tied low in applications that do not use the receive side elastic store. See section 20 on page 129 for details on 4.096

MHz and 8.192 MHz operation using the Interleave Bus Option.

Signal Name:

RSIG

Signal Description:

Receive Signaling Output

Signal Type:

Output

Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled.

Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RLOS/LOTC

Signal Description:

Receive Loss of Sync / Loss of Transmit Clock

Signal Type:

Output

A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the

synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 msec.

Signal Name:

RCL

Signal Description:

Receive Carrier Loss

Signal Type:

Output

Set high when the line interface detects a carrier loss.

Signal Name:

RSIGF

Signal Description:

Receive Signaling Freeze

Signal Type:

Output

Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of

the condition.

4.1.2 RECEIVE SIDE PINS (cont.)

Signal Name:

8MCLK

Signal Description:

8 MHz Clock

Signal Type:

Output

An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.

Signal Name:

Signal Description:

Signal Type:

RPOSO

Receive Positive Data Input

Output

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