DS21554 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS21554

DS21354 (3.3V) and DS21554 (5V) E1 Single Chip Transceivers (SCT)

Dallas Semiconductor -> Maxim Integrated 

4.1.2 Receive Side Pins

Signal Name:

RLINK

Signal Description: Receive Link Data

Signal Type:

Output

Updated with the full recovered E1 data stream on the rising edge of RCLK.

DS21354 & DS21554

Signal Name:

RLCLK

Signal Description: Receive Link Clock

Signal Type:

Output

4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 15 for details.

Signal Name:

RCLK

Signal Description: Receive Clock

Signal Type:

Output

2.048 MHz clock that is used to clock data through the receive side framer.

Signal Name:

RCHCLK

Signal Description: Receive Channel Clock

Signal Type:

Output

A 256 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the

receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is

enabled. Useful for parallel to serial conversion of channel data.

Signal Name:

RCHBLK

Signal Description: Receive Channel Block

Signal Type:

Output

A user programmable output that can be forced high or low during any of the 32 E1 channels.

Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK

when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD

controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps service, 768

kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for

external per–channel loopback, and for per–channel conditioning. See Section 12 for details.

Signal Name:

RSER

Signal Description: Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RSYNC

Signal Description: Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC

multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an

input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.

18 of 117

Share Link: