DS2196
1 INTRODUCTION
The DS2196 is a derivative of the DS21352 T1 Single Chip Transceiver. The feature set has been
optimized for transport applications commonly found in T1 transmission equipment. The DS2196
register map and register bit definitions are compatible with the DS21352/DS21552 allowing for easy
migration to the DS2196. Interface designs requiring per channel code insertion, elastic stores, and ANSI
1’s density monitoring should use the DS21352 or DS21552.
1.1 FEATURE HIGHLIGHTS
• Main Features
Two full featured independent framers
Short / long haul line interface unit (LIU)
100-pin LQFP small package
3.3V operation with 5V tolerant I/O
• 8–bit Parallel Control Port
Multiplexed or non-multiplexed buses
Intel or Motorola formats
Polled or Interrupt environments
• HDLC Support
Two independent HDLC controllers
64 byte RX & TX buffers
Access FDL or single / multiple DS0 channels
• ANSI T1.403-1998 Support
NPRMs
SPRMs
RAI-CI detection and generation
AIS-CI detection and generation
• Format Conversion
D4 to ESF framing
ESF to D4 framing
• Line Interface Unit
Long & Short Haul support
Receive sensitivity: 0 to –36dB
32–bit or 128–bit crystal–less jitter attenuator
DSX-1 and CSU line build out options
Provisions for custom waveform generation
• DS1 Idle Code Generation
User defined
Fixed 7F Hex
Digital Milliwatt
• In-Band Repeating Pattern Generator and Detector
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