DS1994
Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES
VPULLUP
VPULLUP MIN
VIH MIN
MASTER TX
"RESET PULSE"
MASTER RX "PRESENCE PULSE"
tRSTH
VIL MAX
0V
RESISTOR
MASTER
DS1994
tRSTL
tR
tPDH
480µs tRSTL < *
480µs tRSTH < **
15µs tPDH < 60µs
60 tPDL < 240µs
tPDL
* In order not to mask interrup signaling
by other devices on the 1-Wire bus, tRSTL
+ tR should always be less than 960 us.
** Includes recovery time
Figure 11. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
RESISTOR
MASTER
tSLOT
DS1994
Sampling Window
t LOW1
15µs
60µs
60µs tSLOT < 120µs
1µs tLOW1 < 15µs
1µs tREC <
tREC
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