DS1977-F5 Просмотр технического описания (PDF) - Maxim Integrated
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DS1977-F5 Datasheet PDF : 29 Pages
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DS1977
PARAMETER
Presence Detect
Sample Time
I/O Pin, 1-Wire Write
Write-0 Low Time
Write-1 Low Time
I/O Pin, 1-Wire Read
Read Low Time
Read Sample Time
I/O Pin, Strong Pullup
Strong Pullup Read
Strong Pullup Write
Strong Pullup password
verification
EEPROM
Programming Current
Write/Erase Cycles
Data Retention
SYMBOL
tMSP
tW0L
tW1L
tRL
tMSR
tSPUR
tSPUW
tSPUV
ILPROG
NCYCLE
tRET
CONDITIONS
Standard speed, VPUP > 4.5V
(Note 1)
Standard speed (Note 1)
Overdrive speed (Note 1)
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
Standard speed (Notes 1, 13)
Overdrive speed (Notes 1, 13)
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
Standard speed,
VPUP > 4.5V (Notes 1, 14)
Standard speed (Notes 1, 14)
Overdrive speed (Notes 1, 14)
(Note 1)
(Note 1)
(Note 1)
MIN
65
68
7.5
60
6
5
1
5
1
tRL +
tRL +
tRL +
2.64
22.46
0.62
100k
10
TYP
MAX
75
75
10.5
120
16
15
2
15 -
2-
20
15
2
UNITS
µs
µs
µs
µs
µs
ms
ms
ms
7
mA
—
years
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the data pin could be 5nF when power is first applied.
VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and VTL
maximum specifications are valid at VPUPMAX (5.25V). In any case, VTL < VTH < VPUP.
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached before.
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%
of VPUP and the time at which the voltage is 10% of VPUP.
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum
duration for the master to pull the line low is tW1LMAX + tF - and tW0LMAX + tF - respectively.
in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input-high threshold of
the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Parameter
Name
tSLOT (incl. tREC)
tRSTL
tPDH
tPDL
tW0L
Standard Values
Standard Speed
Overdrive Speed
min
max
min
max
61µs
(undef.) 7µs
(undef.)
480µs (undef.) 48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs 8µs
24µs
60µs
120µs 6µs
16µs
DS1977 Values
Standard Speed
Overdrive Speed
min
max
min
max
65µs1)
(undef.) 8µs1)
(undef.)
480µs 640µs 48µs
80µs
15µs
60µs
2.5µs
6.5µs
60µs
240µs 8µs
24µs
60µs
120µs 6µs
16µs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
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