NOTES:
1. All voltages are referenced to ground.
DS1985
2. VPUP = external pullup voltage. If VPUP is lower than 3.0V the first byte read (any read command)
may not reproduce the correct memory contents. Therefore, under low voltage conditions, it is
recommended to set either the most significant bit or all five most significant bits of TA2 to 1.
Internal circuitry of the chip will force these five bits back to 0 before they are shifted in the address
counter and CRC generator.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 µs of this falling edge and will remain valid for 14 µs minimum. (15
µs total from falling edge on 1-Wire bus.)
6. VIH is a function of the external pullup resistor and VPUP .
7. 30 nanocoulombs per 72 time slots @ 5.0V.
8. At VCC =5.0V with a 5kΩ pullup to VCC and a maximum time slot of 120 µs.
9. Capacitance on the data pin could be 800 pF when power is first applied. If a 5kΩ resistor is used to
pull up the data line to VCC, 5 µs after power has been applied the parasite capacitance will not affect
normal communications.
10. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a presence pulse.
25 of 25