DS1985
(Figure 11) should be applied for 480 µs, after which the bus master returns the data line to an idle high
state controlled by the pullup resistor. Note that due to the high voltage programming requirements for
any 1-Wire EPROM device, it is not possible to multidrop non-EPROM based 1-Wire devices with the
DS1985 during programming. An internal diode within the non-EPROM based 1-Wire devices will
attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
RESISTOR
MASTER
DS1985
480 µs ≤ tRSTL < ∞ *
480 µs ≤ tRSTH < ∞ (includes recovery time)
15 µs ≤ tPDH < 60 µs
60 µs ≤ tPDL < 240 µs
∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960 µs.
READ/WRITE TIMING DIAGRAM Figure 10
Write-1 Time Slot
RESISTOR
MASTER
60 µs ≤ tSLOT < 120 µs
1 µs ≤ tLOW1 < 15 µs
1 µs ≤ tREC < ∞
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