DS1977 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1977

32KB EEPROM iButton

Dallas Semiconductor -> Maxim Integrated 

Version Register (DS1977)

ADDR b7

b6

b5

b4

b3

b2

b1

b0

N/A VER2 VER1 VER0

0

0

0

0

0

Bit Description

VER: Chip Revision

Indicator

Bit(s)

b5 to

b7

Definition

These hard-wired bits are used to distinguish different

revisions or chips that use the same 1-Wire family code

as the DS1977. The initial version of the DS1977 chip will

have all revision bits set to 0.

Figure 4. ADDRESS REGISTERS

TARGET ADDRESS (TA1) T7

T6

T5

T4

T3

T2

T1

T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9

T8

ENDING ADDRESS WITH

DATA STATUS (E/S) AA

PF

E5

E4

E3

E2

E1

E0

(READ ONLY)

Address Registers and Transfer Status

Because of the serial data transfer, the DS1977 iButton employs three address registers, called

TA1, TA2 and E/S (Figure ??). Registers TA1 and TA2 must be loaded with the target address to

which the data will be written or from which data will be sent to the 1-Wire master upon a Read

command. Register E/S acts like a byte counter and Transfer Status register. It is used to verify

data integrity with write commands. Therefore, the 1-Wire master only has read access to this

register. The lower six bits of the E/S register indicate the address of the last byte that has been

written to the scratchpad. This address is called Ending Offset. Bit 6 of the E/S register, called PF,

is set if the number of data bits sent by the 1-Wire master is not an integer multiple of 8 or if the

data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear

the PF bit. Note that the lowest six bits of the target address also determine the address within the

scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the

target address (TA1) for a Write command is 103Ch for example, then the scratchpad will store

incoming data beginning at the byte offset 3Ch and will be full after only four bytes. The

corresponding ending offset in this example is 3Fh. For best economy of speed and efficiency, the

target address for writing should point to the beginning of a new page, i.e., the byte offset will be

0. Thus the full 64-byte capacity of the scratchpad is available, resulting also in the ending offset

of 3Fh. However, it is possible to write one or several contiguous bytes somewhere within a page.

The ending offset together with the Partial Flag support the 1-Wire master checking the data

integrity after a Write command. The highest valued bit of the E/S register, called AA is valid only

if the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. The AA bit is cleared when

the device receives a write scratchpad command.

Page 4

1/31/03

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