DS1808 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS1808

Dual Log Digital Potentiometer

Dallas Semiconductor -> Maxim Integrated 

DS1808

NOTES:

1. All voltages are referenced to ground.

2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.

3. The value of VDD should never exceed VCC, including during power-ups. VCC must be applied before

either VDD or VB. VDD and VB can then follow in any order.

4. ISTBY specified for VDD equal to 5.0V. Control port logic pins are driven to the appropriate logic

levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VDD for the

corresponding inactive state.

5. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of

the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the

next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is

released.

6. After this period, the first clock pulse is generated.

7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCL signal.

8. CB – Total capacitance of one bus line in picofarads, timing referenced to (0.9)(VDD) and (0.1)(VDD).

9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.

10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper

positions.

11. When used as a rheostat or variable resistor the resistance temperature coefficient is: 750ppm/°C.

When used as a voltage divider or potentiometer, the output voltage temperature coefficient

approaches 30 ppm/°C.

12. ICC specified with SDA pin open.

13. Maximum ICC is dependent on clock rates.

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