DM9000B Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.
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DM9000B Datasheet PDF : 56 Pages
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DM9000B
Ethernet Controller with General Processor Interface
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode)
Bit
Name
Type
Description
7:6 RESERVED 0,RO Reserved
5
LINKEN
P0,RW
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4
SAMPLEEN
P0,RW
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
3
MAGICEN
P0,RW
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
2
LINKST
P0,RO
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
1
SAMPLEST
P0,RO
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
0
MAGICST
P0,RO
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit
Name
Default
7:0
PAB5
E,RW Physical Address Byte 5 (15H)
7:0
PAB4
E,RW Physical Address Byte 4 (14H)
7:0
PAB3
E,RW Physical Address Byte 3 (13H)
7:0
PAB2
E,RW Physical Address Byte 2 (12H)
7:0
PAB1
E,RW Physical Address Byte 1 (11H)
7:0
PAB0
E,RW Physical Address Byte 0 (10H)
Description
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
X,RW Multicast Address Byte 7
7:0
MAB6
X,RW Multicast Address Byte 6
7:0
MAB5
X,RW Multicast Address Byte 5
7:0
MAB4
X,RW Multicast Address Byte 4
7:0
MAB3
X,RW Multicast Address Byte 3
7:0
MAB2
X,RW Multicast Address Byte 2
7:0
MAB1
X,RW Multicast Address Byte 1
7:0
MAB0
X,RW Multicast Address Byte 0
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
Description
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, for 16 bit mode, see reg . 34H)
Bit
Name
Default
Description
7 RESERVED PH0,RO Reserved
6:4
GPC64
P,
111,RO
General Purpose Control 6~4
Define the input/output direction of pins GP6~4 respectively.
These bits are all forced to “1”s, so pins GP6~4 are output only.
General Purpose Control 3~1
3:1
GPC31
P, Define the input/output direction of pins GP 3~1 respectively.
000,RW When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
0 RESERVED P1,RO Reserved
Final
19
Version: DM9000B-13-DS-F02
June 4, 2009
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