DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DMC73C168 Просмотр технического описания (PDF) - Daewoo Semiconductor

Номер в каталоге
Компоненты Описание
производитель
DMC73C168
Daewoo
Daewoo Semiconductor Daewoo
DMC73C168 Datasheet PDF : 82 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
8Bit Single Chip Microcontroller
33
DMC73C168
FSELn :
BEEP Frequency select :
FSEL1
0
0
1
1
FSEL0
0
1
0
1
BEEP FREQ.
417Hz (2/3 Duty)
1KHz (1/2 Duty)
1.25 KHz (1/2 Duty)
2.5 KHz (1/2 Duty)
9) Peripheral RAM register
PF NAME : PRAM 0-127 : Peripheral RAM register
P64-P191 R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
>140 ~ READ
Peripheral RAM register
>01BF WRITE
Peripheral RAM register
RESET VALUE
X
X
X
X
X
X
BIT 1
X
BIT 0
X
These peripheral RAM region is >140 (hex) to >01BF (hex), and size is 128 bytes.
4.8 Interrupt and Reset Priorities
The DMC73C168 has priority servicing of interrupt levels and RESET. These levels are defined as
shown in Table 4-8. The TRAP instruction branch to a two bytes location in a reserved section of
memory called the TRAP Vector Table. As shown in Figure 4-8, each trap location stores a 16-bit
address which references either reset function (TRAP0), one of the seven interrupt service routine
(TRAP1-INT1, TRAP2-INT2, TRAP3-INT3, TRAP4-INT4, TRAP5-INT5, TRAP6-INT6, TRAP7-INT7),
or a subroutine (TRAP8-23).
Once INTn has been acknowledged by the CPU, the corresponding INTn Flag flip flop is cleared.
The CPU then pushes the contents of the Status Register and Program Counter (MSB and LSB)
onto the stack and zeros the Status Register, including the global Interrupt Enable (I) bit. the CPU
reads an interrupt code from the interrupt logic and branches to the address contained in the
corresponding interrupt vector location in memory.
The interrupt service routine can explicitly enable nested interrupt by executing the EINT instruction
to directly set I bit in the Status Register to a one, thus permitting nested interrupt to be recognized.
When the nested interrupt service routine completes, it returns to the previous interrupt service
routine by executing the RETI instruction.
Level
0
1
2
3
4-0
Name
RESET
INT1 External (CE)
INT2 Timer 1
INT3 External
INT4 External
Trigger Factor
Active Low/Level Sensitive
Program Selectable
Timer 1 through '>0000'
Program Selectable
Program Selectable
Vector
MSB LSB
>FFFE >FFFF
>FFFC >FFFD
>FFFA >FFFB
>FFF8 >FFF9
>FFF6 >FFF7
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]