CY7C68013-56LFC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C68013-56LFC Datasheet PDF : 48 Pages
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CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128 100 56 56
TQFP TQFP SSOP QFN Name
Type
110 88
PE2 or
T2OUT
I/O/Z
111 89
PE3 or
RXD0OUT
I/O/Z
112 90
PE4 or
RXD1OUT
I/O/Z
113 91
114 92
115 93
PE5 or
INT6
I/O/Z
PE6 or
T2EX
I/O/Z
PE7 or
I/O/Z
GPIFADR8
Default
Description
I
(PE2)
Multiplexed pin whose function is selected by the PORTECFG.2
bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2.
T2OUT is active (HIGH) for one clock cycle when Timer/Counter
2 overflows.
I
(PE3)
Multiplexed pin whose function is selected by the PORTECFG.3
bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
I
(PE4)
Multiplexed pin whose function is selected by the PORTECFG.4
bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in Mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In Modes
1, 2, and 3, this pin is HIGH.
I
(PE5)
Multiplexed pin whose function is selected by the PORTECFG.5
bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin
is edge-sensitive, active HIGH.
I
(PE6)
Multiplexed pin whose function is selected by the PORTECFG.6
bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX
reloads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
I
(PE7)
Multiplexed pin whose function is selected by the PORTECFG.7
bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4
3
5
4
6
5
7
6
8
7
9
8
8 1 RDY0 or
SLRD
9 2 RDY1 or
SLWR
RDY2
RDY3
RDY4
RDY5
Input
Input
Input
Input
Input
Input
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPOLAR.3) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
N/A RDY2 is a GPIF input signal.
N/A RDY3 is a GPIF input signal.
N/A RDY4 is a GPIF input signal.
N/A RDY5 is a GPIF input signal.
Document #: 38-08012 Rev. *E
Page 20 of 48
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