CY7C68013-128AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C68013-128AC Datasheet PDF : 48 Pages
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CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128 100 56 56
TQFP TQFP SSOP QFN Name
Type
77 62
PC5 or
I/O/Z
GPIFADR5
78 63
PC6 or
I/O/Z
GPIFADR6
79 64
PC7 or
I/O/Z
GPIFADR7
PORT D
102 80
52 45 PD0 or
FD[8]
I/O/Z
103 81
53 46 PD1 or
FD[9]
I/O/Z
104 82
54 47 PD2 or
FD[10]
I/O/Z
105 83
55 48 PD3 or
FD[11]
I/O/Z
121 95
56 49 PD4 or
FD[12]
I/O/Z
122 96
1 50 PD5 or
FD[13]
I/O/Z
123 97
2 51 PD6 or
FD[14]
I/O/Z
124 98
3 52 PD7 or
FD[15]
I/O/Z
Port E
108 86
PE0 or
T0OUT
I/O/Z
109 87
PE1 or
T1OUT
I/O/Z
Default
Description
I Multiplexed pin whose function is selected by PORTCCFG.5
(PC5) PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.6
(PC6) PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.7
(PC7) PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD0) and EPxFIFCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD1) and EPxFIFCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD2) and EPxFIFCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD3) and EPxFIFCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD4) and EPxFIFCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD5) and EPxFIFCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD6) and EPxFIFCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD7) and EPxFIFCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
I
(PE0)
Multiplexed pin whose function is selected by the PORTECFG.0
bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
I
(PE1)
Multiplexed pin whose function is selected by the PORTECFG.1
bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
Document #: 38-08012 Rev. *E
Page 19 of 48
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