CY7C63001-WC Просмотр технического описания (PDF) - Cypress Semiconductor
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производитель
CY7C63001-WC Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
.
Logic Block Diagram
6 MHz
RESONATOR
R/CEXT
OSC
AAAAAAAAAAAAAAAAAAAAIAAAAAAAAAANNAAAAAAAAAAAAAAAAAAAASOAAAAAAAAAATAAAAAAAAAAWAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA<NAAAAAAAAAATAAAAAAAAAATAAAAAAAAAAM-AAAAAAAAAAOAAAAAAAAAA>AAAAAAAAAANAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
RAM
128 Byte
8-bit
Timer
EPROM
2K/4K Byte
Power
on Reset
Watch
Dog
Timer
8-bit
RISC
core
Interrupt
Controller
USB
Engine
PORT
0
PORT
1
D+,D–
VCC/VSS
P0.0–P0.7
P1.0–P1.7
PinConfigurations (Top View)
18-pin
DIP/
Windowed CerDIP
P0.0 1
P0.1 2
P0.2 3
P0.3 4
P1.0 5
VSS 6
VPP 7
CEXT 8
XTALIN 9
18 P0.4
17 P0.5
16 P0.6
15 P0.7
14 P1.1
13 D+
12 D-
11 VCC
10 XTALOUT
20-pin
DIP/SOIC/
Windowed CerDIP
P0.0 1
P0.1 2
P0.2 3
P0.3 4
P1.0 5
P1.2 6
VSS 7
VPP 8
CEXT 9
XTALIN 10
20 P0.4
19 P0.5
18 P0.6
17 P0.7
16 P1.1
15 P1.3
14 D+
13 D-
12 VCC
11 XTALOUT
24-pin
SOIC/
Windowed CerDIP
P0.0 1
P0.1 2
P0.2 3
P0.3 4
P1.0 5
P1.2 6
P1.4 7
P1.6 8
VSS 9
VPP 10
CEXT 11
XTALIN 12
24 P0.4
23 P0.5
22 P0.6
21 P0.7
20 P1.1
19 P1.3
18 P1.5
17 P1.7
16 D+
15 D–
14 VCC
13 XTALOUT
6311–1
5
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