CY7C63001-WC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C63001-WC

Universal Serial Bus Microcontroller

Cypress Semiconductor 

PRELIMINARY

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

5.3.2 Watch Dog Reset (WDR)

The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit of the 4-bit Watch Dog Timer Register transitions from

LOW to HIGH. Writing any value to the write-only Watch Dog Restart Register at 0x21 will clear the timer. The Watch Dog timer

is clocked by a 1.024 ms clock from the free running timer. If 8 clocks occur between writes to the timer, a WDR occurs. Bit 6 of

the Status and Control Register will be set to record the event. A Watch Dog Timer Reset lasts for 8.192 ms after which the

microcontroller begins execution at ROM address 0x00. The USB transmitter is disabled by a Watch Dog Reset because the

USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The

transmitter remains disabled until the WDR bit in the Status and Control Register is reset to 0 by firmware.

8.192 ms

8.192 ms

last write to

Watchdog Timer

Register

No write to WDT

register, so WDR

goes high

Execution begins at

Reset Vector 0X00

Figure 5-4. Watch Dog Reset (WDR)

5.3.3 USB Bus Reset

The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists for longer than 8 micro-seconds.

SE0 is defined as the condition in which both the D+ line and the D– line are LOW. Bit 5 of the Status and Control Register will

be set to record this event. If the USB reset happens while the device is suspended (such as after a POR), the suspend condition

will be cleared and the clock oscillator will be restarted. However, the microcontroller is not released until the USB reset is

removed.

5.4 On-chip Timer

The USB Controller is equipped with an 8-bit free-running timer driven by a clock one-sixth the crystal frequency. Bits 0 through

7 of the counter are readable from the read-only Timer Register located at I/O address 0x23. The Timer Register is cleared during

a Power-On Reset. Figure 5-5 illustrates the format of this register and Figure 5-6 is its block diagram.

With a 6 MHz crystal, the timer resolution is 1 µs.

The timer generates two interrupts: the 128 µs interrupt and the 1.024 ms interrupt.

7

R

Count 7

6

R

Count 6

5

R

Count 5

4

R

Count 4

3

R

Count 3

2

R

Count 2

Figure 5-5. Timer Register (Address 0x23)

1

R

Count 1

0

R

Count 0

11

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