CY7C63001-WC Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C63001-WC Datasheet PDF : 27 Pages
| |||
PRELIMINARY
CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
Table 5-1. I/O Register Summary (continued)
Register Name
I/O Address
Global Interrupt Enable
Watch Dog Timer
0x20
0x21
Cext Clear
Timer
Port 0 Isink
0x22
0x23
0x30-0x37
Port 1 Isink
0x38-0x3B
Status & Control
0xFF
Read/Write
R/W
W
R/W
R
W
W
R/W
Function
Global Interrupt Enable
Watch Dog Timer clear
External R-C Timing circuit control
Free-running timer
Input sink current control for Port 0 pins. There is one
Isink register for each pin. Address of the Isink register
for pin 0 is located at 0x30 and the register address
for pin 7 is located at 0x37
Input sink current control for Port 1 pins. There is one
Isink register for each pin. Address of the Isink register
for pin 0 is located at 0x38 and the register address
for pin 3 is located at 0x3B
Processor status and control
5.3 Reset
The USB Controller supports three types of resets. All registers are restored to their default states during a reset. The USB Device
Address is set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) is set to 0x00 and the Data Stack
Pointer (DSP) is set to 0x00. The user should set the DSP to location 0x70 to reserve 16 bytes of FIFO space. The assembly
instructions to do so are:
Mov A, 70h ; Move 70 hex into Accumulator, use 70 instead of 6F because the dsp is
; always decremented by 1 before data transfer in the PUSH instruction
Swap A, dsp ; Move Accumulator value into dsp
The three reset types are:
1. Power On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Reset
The occurrence of a reset is recorded in the Status and Control Register located at I/O address 0xFF (Figure 5-3). Reading and
writing this register are supported by the IORD and IOWR instructions. Bits 1, 2, and 7 are reserved and must be written as zeros
during a write. During a read, reserved bit positions should be ignored. Bits 4, 5, and 6 are used to record the occurrence of POR,
USB and WDR Reset respectively. The firmware can interrogate these bits to determine the cause of a reset. Bit 0 is the “Run”
control, clearing this bit will stop the microcontroller. Once this bit is set to low, only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address 0X00 after a reset unless the Suspend bit (bit 3) of the Status and
Control Register is set. Setting the Suspend bit stops the clock oscillator and the interrupt timers as well as powering-down the
microcontroller. The detection of any USB activity will terminate the suspend condition.
7
6
5
4
3
2
1
0
W
R/W
R/W
R/W
R/W
W
W
R/W
Reserved Watch Dog USB Reset Power-on
Suspend
Reserved
Reserved
Run
Reset
Reset
Figure 5-3. Status and Control Register (Address 0xFF)
5.3.1 Power-On Reset (POR)
Power On Reset (POR) occurs every time the power to the device is switched on. Bit 4 of the Status and Control Register is set
to record this event (the register contents are set to 00011001 by the POR). The USB Controller is placed in suspended mode at
the end of POR to conserve power (most device functions such as the clock oscillator, the timers, and the interrupt logic are turned
off in the suspend mode). Only a non-idle USB Bus state will terminate the suspend mode and begin normal operations.
10
Share Link: 