CY7C63001A-SXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C63001A-SXC Datasheet PDF : 25 Pages
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CY7C63001A
CY7C63101A
6.5 On-Chip Timer
The USB Controller is equipped with a free-running timer
driven by a clock one-sixth the resonator frequency. Bits 0
through 7 of the counter are readable from the read-only Timer
Register located at I/O address 0x23. The Timer Register is
cleared during a Power-On Reset and whenever Suspend
mode is entered. Figure 6-6 illustrates the format of this
register and Figure 6-7 is its block diagram.
With a 6 MHz resonator, the timer resolution is 1 µs.
The timer generates two interrupts: the 128-µs interrupt and
the 1.024-ms interrupt.
Figure 6-6. Timer Register (Address 0x23)
b7
b6
b5
b4
b3
b2
b1
b0
T.7
T.6
T.5
T.4
T.3
T.2
T.1
T.0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
1.024-ms interrupt
128-ms interrupt
9 8 7 6 54 32 1 0
Resonator Clock/6
Figure 6-7. Timer Block Diagram
8
To Timer Register
6.6 General Purpose I/O Ports
Interface with peripherals is conducted via as many as 16
GPIO signals. These signals are divided into two ports: Port 0
and Port 1. Port 0 contains eight lines (P0.0–P0.7) and Port 1
contains up to eight lines (P1.0–P1.7). The number of external
I/O pins depends on the package type. Both ports can be
accessed by the IORD, IOWR, and IOWX instructions. The
Port 0 data register is located at I/O address 0x00 while the
Port 1 data register is located at I/O address 0x01. The
contents of both registers are set HIGH during a reset. Refer
to Figures 6-8 and 6-9 for the formats of the data registers. In
addition to supporting general input/output functions, each I/O
line can trigger an interrupt to the microcontroller. Please refer
to the interrupt section for more details.
b7
P0.7
R/W
1
b6
P0.6
R/W
1
b5
b4
b3
b2
P0.5
P0.4
P0.3
P0.2
R/W
R/W
R/W
R/W
1
1
1
1
Figure 6-8. Port 0 Data Register (Address 0x00)
b1
P0.1
R/W
1
b0
P0.0
R/W
1
b7
P1.7
R/W
1
b6
P1.6
R/W
1
b5
b4
b3
b2
P1.5
P1.4
P1.3
P1.2
R/W
R/W
R/W
R/W
1
1
1
1
Figure 6-9. Port 1 Data Register (Address 0x01)
b1
P1.1
R/W
1
b0
P1.0
R/W
1
Document #: 38-08026 Rev. *A
Page 8 of 25
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