CY7C63001A-SXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C63001A-SXC Datasheet PDF : 25 Pages
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CY7C63001A
CY7C63101A
Table 6-1. I/O Register Summary (continued)
Register Name I/O Address
P1 Isink
0x38-0x3F
Read/Write
W
SCR
0xFF
R/W
Function
Page
Input sink current control for Port 1 pins. There is one Figure 6-13
Isink register for each pin. Address of the Isink register
for pin 0 is located at 0x38 and the register address for
pin 7 is located at 0x3F. The number of Port 1 pins
depends on package type.
Processor status and control register
Figure 6-3
6.3 Reset
The USB Controller supports three types of resets. All
registers are restored to theirWatchdog default states during a
reset. The USB Device Address is set to 0 and all interrupts
are disabled. In addition, the Program Stack Pointer (PSP) is
set to 0x00 and the Data Stack Pointer (DSP) is set to 0x00.
The user should set the DSP to a location such as 0x70 to
reserve 16 bytes of USB FIFO space. The assembly instruc-
tions to do so are:
MOV A, 70h
; Move 70 hex into Accumulator, use 70
instead of 6F because the dsp is
; always decremented by 1 before the
data transfer of the PUSH instruction occurs
SWAP A, DSP ; Move Accumulator value into dsp
The three reset types are:
1. Power-On Reset (POR)
2. Watchdog Reset (WDR)
3. USB Reset
The occurrence of a reset is recorded in the Status and Control
Register located at I/O address 0xFF (Figure 6-3). Reading
and writing this register are supported by the IORD and IOWR
instructions. Bits 1, 2, and 7 are reserved and must be written
as zeros during a write. During a read, reserved bit positions
should be ignored. Bits 4, 5, and 6 are used to record the
occurrence of POR, USB, and WDR Reset respectively. The
firmware can interrogate these bits to determine the cause of
a reset. If a Watchdog Reset occurs, firmware must clear the
WDR bit (bit 6) in the Status and Control Register to re-enable
the USB transmitter (please refer to the Watchdog Reset
section for further details). Bit 0, the “Run” control, is set to 1
at POR. Clearing this bit stops the microcontroller (firmware
normally should not clear this bit). Once this bit is set to LOW,
only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address
0x00 after a reset unless the Suspend bit (bit 3) of the Status
and Control Register is set. Setting the Suspend bit stops the
clock oscillator and the interrupt timers and powers down the
microcontroller. The detection of any USB activity, the occur-
rence of a GPIO Interrupt, or the occurrence of the Cext
Interrupt terminates the suspend condition.
b7
Reserved
0
b6
WDR
R/W
0
b5
USBR
b4
POR
b3
SUSPEND
b2
Reserved
b1
Reserved
R/W
R/W
R/W
0
1
0
0
0
Figure 6-3. Status and Control Register (SCR – Address 0xFF)
b0
RUN
R/W
1
6.3.1 Power-On Reset
Power-On Reset (POR) occurs every time the power to the
device is switched on. Bit 4 of the Status and Control Register
is set to record this event (the register contents are set to
00011001 by the POR). The USB Controller is placed in
suspended mode at the end of POR to conserve power (the
clock oscillator, the timers, and the interrupt logic are turned
off in suspend mode). After POR, only a non-idle USB Bus
state terminates the suspend mode. The microcontroller then
begins execution from ROM address 0x00.
Document #: 38-08026 Rev. *A
Page 6 of 25
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