CY7C63001A-SXC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C63001A-SXC

Universal Serial Bus Microcontroller

Cypress Semiconductor 

CY7C63001A

CY7C63101A

When servicing an interrupt, the hardware first disables all

interrupts by clearing the Global Interrupt Enable Register.

Next, the interrupt latch of the current interrupt is cleared. This

is followed by a CALL instruction to the ROM address

associated with the interrupt being serviced (i.e., the interrupt

vector). The instruction in the interrupt table is typically a JMP

instruction to the address of the Interrupt Service Routine

(ISR). The user can re-enable interrupts in the interrupt service

routine by writing to the appropriate bits in the Global Interrupt

Enable Register. Interrupts can be nested to a level limited

only by the available stack space.

The Program Counter (PC) value and the Carry and Zero flags

(CF, ZF) are automatically stored onto the Program Stack by

the CALL instruction as part of the interrupt acknowledge

Table 6-3. Interrupt Vector Assignments

process. The user firmware is responsible for ensuring that the

processor state is preserved and restored during an interrupt.

For example the PUSH A instruction should be used as the

first command in the ISR to save the accumulator value. And,

the IPRET instruction should be used to exit the ISR with the

accumulator value restored and interrupts enabled. The PC,

CF, and ZF are restored when the IPRET or RET instructions

are executed.

The Interrupt Vectors supported by the USB Controller are

listed in Table 6-3. Interrupt Vector 0 (Reset) has the highest

priority, Interrupt Vector 7 has the lowest priority. Because the

JMP instruction is two bytes long, the interrupt vectors occupy

two bytes.

Interrupt Priority

0 (Highest)

1

2

ROM Address

0x00

0x02

0x04

Function

Reset

128-µs timer interrupt

1.024-ms timer interrupt

3

4

5

6

7 (Lowest)

0x06

0x08

0x0A

0x0C

0x0E

USB endpoint 0 interrupt

USB endpoint 1 interrupt

Reserved

GPIO interrupt

Wake-up interrupt

6.8.1 Interrupt Latency

Interrupt latency can be calculated from the following

equation:

Interrupt Latency =

(Number of clock cycles remaining in the

current instruction) + (10 clock cycles for

the CALL instruction) + (5 clock cycles

for the JMP instruction)

For example, if a 5-clock-cycle instruction such as JC is being

executed when an interrupt occurs, the first instruction of the

Interrupt Service Routine executes a minimum of 16 clock

cycles (1+10+5) or a maximum of 20 clock cycles (5+10+5)

after the interrupt is issued. Therefore, the interrupt latency in

this example will be = 20 clock periods = 20 / (12 MHz) = 1.667

µs. The interrupt latches are sampled at the rising edge of the

last clock cycle in the current instruction.

Logic 1

128-ms

Interrupt

CLR

DQ

CLK

Enable [1]

Global

Interrupt

Enable

Register

CLR

Interrupt

Acknowledge

Enable [7:0]

Logic 1

GPIO

Interrupt

CLR

DQ

CLK

Enable [6]

CLR

Logic 1 D

Q Enable [7]

CEXT

CLK

128-ms CLR

128-ms IRQ

1-ms CLR

1-ms IRQ

End P0 CLR

End P0 IRQ

End P1 CLR

End P1 IRQ

GPIO CLR

GPIO IRQ

IRQ

Interrupt

Vector

Wake-up CLR

Wake-up IRQ

Interrupt

Priority

Encoder

Figure 6-16. Interrupt Controller Logic Block Diagram

Document #: 38-08026 Rev. *A

Page 11 of 25

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