CY7C63001A-SXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C63001A-SXC Datasheet PDF : 25 Pages
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CY7C63001A
CY7C63101A
b7
PULL1.7
W
0x
b6
PULL1.6
W
0
b5
b4
b3
b2
PULL1.5
PULL1.4
PULL1.3
PULL1.2
W
W
W
W
0
0
0
0
Figure 6-12. Port 1 Pull-up Register (Address 0x09)
b1
PULL1.1
W
0
b0
PULL1.0
W
0
Writing a “0” to the Data Register drives the output LOW.
Instead of providing a fixed output drive, the USB Controller
allows the user to select an output sink current level for each
I/O pin. The sink current of each output is controlled by a
dedicated Port Isink Register. The lower four bits of this
register contain a code selecting one of sixteen sink current
levels. The upper four bits of the register are ignored. The
format of the Port Isink Register is shown in Figure 6-13.
b7
Reserved
W
x
b6
Reserved
W
x
b5
b4
b3
b2
Reserved
UNUSED
ISINK3
ISINK2
W
W
W
W
x
x
x
x
Figure 6-13. Port Isink Register for One GPIO Line
b1
ISINK1
W
x
b0
ISINK0
W
x
Port 0 is a low-current port suitable for connecting photo
transistors. Port 1 is a high current port capable of driving
LEDs. See section 8.0 for current ranges. 0000 is the lowest
drive strength. 1111 is the highest.
The write-only sink current control registers for Port 0 outputs
are assigned from I/O address 0x30 to 0x37 with the control
bits for P00 starting at 0x30. Port 1 sink current control
registers are assigned from I/O address 0x38 to 0x3F with the
control bits for P10 starting at 0x38. All sink current control
registers are cleared during a reset, resulting in the minimum
current sink setting.
6.7 XTALIN/XTALOUT
The XTALIN and XTALOUT pins support connection of a 6-
MHz ceramic resonator. The feedback capacitors and bias
resistor are internal to the IC, as shown in Figure 6-14 Leave
XTALOUT unconnected when driving XTALIN from an external
oscillator.
XTALOUT
clk1x
(to USB SIE)
clk2x
(to Microcontroller)
Clock
Doubler
30 pF
30 pF
XTALIN
Figure 6-14. Clock Oscillator On-chip Circuit
6.8 Interrupts
Interrupts are generated by the General Purpose I/O lines, the
Cext pin, the internal timer, and the USB engine. All interrupts
are maskable by the Global Interrupt Enable Register. Access
to this register is accomplished via IORD, IOWR, and IOWX
instructions to address 0x20. Writing a “1” to a bit position
enables the interrupt associated with that position. During a
reset, the contents of the Interrupt Enable Register are
cleared, disabling all interrupts. Figure 6-15 illustrates the
format of the Global Interrupt Enable Register.
b7
CEXTIE
R/W
0
b6
b5
b4
b3
b2
b1
GPIOIE
Reserved
EP1IE
EP0IE
1024IE
128IE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Figure 6-15. Global Interrupt Enable Register (GIER – Address 0x20)
b0
Reserved
0
The interrupt controller contains a separate latch for each
interrupt. See Figure 6-16 for the logic block diagram for the
interrupt controller. When an interrupt is generated, it is
latched as a pending interrupt. It stays as a pending interrupt
until it is serviced or a reset occurs. A pending interrupt only
generates an interrupt request if it is enabled in the Global
Interrupt Enable Register. The highest priority interrupt
request is serviced following the execution of the current
instruction.
Document #: 38-08026 Rev. *A
Page 10 of 25
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