CY7C1359A-100AC Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1359A-100AC

256K x 18 Synchronous-Pipelined Cache Tag RAM

Cypress Semiconductor 

CY7C1359A/GVT71256T18

Switching Waveforms

Read Timing with Burst Feature[32, 33]

CLK

ADSP#

ADSC#

ADDRESS

WEL#, WEH#,

BWE#, GW#

CE#

ADV#

OE#

DQ

tS

tH

tS

A1

tH

tKC

tKL

tKH

A2

tS

tS

tH

tKQLZ

tKQ

tOELZ

Q(A1)

tOEQ

tKQ

Q(A2)

Q(A2+1)

SINGLE READ

Q(A2+2)

Q(A2+3) Q(A2) Q(A2+1)

BURST READ

Notes:

32. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.

33. In this timing diagram, it is assumed that DEN is tied to LOW (VSS).

Document #: 38-05120 Rev. **

Page 18 of 24

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