CY7C1328G Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1328G

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Cypress Semiconductor 

CY7C1328G

Document History Page

Document Title: CY7C1328G 4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Document Number: 38-05523

Orig. of

REV. ECN NO. Issue Date Change

Description of Change

**

224371 See ECN RKF New data sheet

*A

288909 See ECN VBL Changed TQFP to PB-Free TQFP in Ordering Information section

*B

333625 See ECN SYT Removed 133-MHz Speed Grade

Changed 166-MHz to 167-MHz Speed bin

Changed the test condition from VDD = Min. to VDD = Max. for VOL in the Electrical

Characteristics table

Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resis-

tance table

*C

419264 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

North First Street” to “198 Champion Court”

Modified test condition from VIH < VDD to VIH < VDD

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering Infor-

mation table

Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information

*D

430373 See ECN NXR Include 133-MHz Speed Grade

Updated the ordering information

*E

480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Updated the Ordering Information table.

Document #: 38-05523 Rev. *E

Page 16 of 16

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