CY7C1328G Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1328G

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read/Write Timing[16, 18, 19]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

ADSC

ADDRESS

A1

tAS tAH

A2

BWE,

BW[A:B]

CE

tCES tCEH

A3

A4

tWES tWEH

CY7C1328G

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

tCO

tDS tDH

High-Z

High-Z

tCLZ

tOEHZ

Q(A1)

Q(A2)

Back-to-Back READs

D(A3)

Single WRITE

tOELZ

Q(A4)

Q(A4+1)

Q(A4+2)

BURST READ

Q(A4+3)

DON’T CARE

UNDEFINED

Notes:

18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

19. GW is HIGH.

D(A5)

D(A6)

Back-to-Back

WRITEs

Document #: 38-05523 Rev. *E

Page 13 of 16

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