80960CF-40(2002) Просмотр технического описания (PDF) - Intel

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80960CF-40
(Rev.:2002)

32-Bit High-Performance Superscalar Embedded Microprocessor

Intel 

80960-40, -33, -25

Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 3 of 3)

Symbol

Parameter (1)

Min

Max

Unit Notes

NOTES:

1. 80960CF-25 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test

Conditions.

2. See Section 4.5.2, A.C. Timing Waveforms for waveforms and definitions.

3. See Figure 16 for capacitive derating information for output delays and hold times.

4. See Figure 17 for capacitive derating information for rise and fall times.

5. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus

Controller Region Table. WAIT never goes active when there are no wait states in an access.

6. N = Number of wait states inserted with READY.

7. Output Data and/or DT/R may be driven indefinitely following a cycle when there is no subsequent bus

activity.

8. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or

hold times to be recognized and for proper operation. However, to ensure recognition of the input at a

particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for

at least two consecutive PCLK2:1 rising edges to be seen by the processor.

9. These specifications are ensured by the processor.

10.These specifications must be met by the system for proper operation of the processor.

11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating

Curves to adjust the timing for PCLK2:1 loading.

12.In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is

operating. When the processor is in reset, the input clock may stop even in 1-x mode.

13.When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation

of less than ± 0.1% between adjacent cycles.

14.In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper

operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET

pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 23.)

15.In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper

operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET

pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 24.)

16.The interrupt pins are synchronized internally by the 80960CF. They have no required setup or hold times

for proper operation. These pins are sampled by the interrupt controller every other clock and must be

active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To ensure

recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive

PCLK2:1 rising edges.

4.5.1

A.C. Test Conditions

The AC Specifications in Section 4.5, “A.C. Specifications” on page 29 are tested with the 50 pF

load shown in Figure 7. Figure 16 shows how timings vary with load capacitance.

Specifications are measured at the 1.5 V crossing point, unless otherwise indicated. Input

waveforms are assumed to have a rise and fall time of < 2 ns from 0.8 V to 2.0 V. See Section 4.5.2,

“A.C. Timing Waveforms” on page 36 for AC specification definitions, test points and

illustrations.

Figure 7. A.C. Test Load

Output Pin

CL

CL = 50 pF for all signals

F_CX008A

Datasheet

35

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