74LVCH32374A Просмотр технического описания (PDF) - Philips Electronics
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74LVCH32374A
Philips Electronics
74LVCH32374A Datasheet PDF : 16 Pages
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Philips Semiconductors
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
Product specification
74LVCH32374A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
VOH
HIGH-level output voltage
VOL
LOW-level output voltage
II
IOZ
Ioff
ICC
∆ICC
IBHL
IBHH
IBHLO
IBHHO
input leakage current
3-state output OFF-state
current
power off leakage supply
current
quiescent supply current
additional quiescent supply
current per input pin
bus hold LOW sustaining
current
bus hold HIGH sustaining
current
bus hold LOW overdrive
current
bus hold HIGH overdrive
current
TEST CONDITIONS
Tamb (°C)
OTHER
VCC (V)
−40 to +85
UNIT
MIN. TYP.(1) MAX.
1.2
VCC
−
−
V
2.7 to 3.6 2.0
−
−
V
1.2
−
−
GND V
2.7 to 3.6 −
−
0.8 V
VI = VIH or VIL
IO = −12 mA
2.7
IO = −100 µA
3.0
IO = −18 mA
3.0
IO = −24 mA
3.0
VI = VIH or VIL
IO = 12 mA
2.7
IO = 100 µA
3.0
IO = 24 mA
3.0
VI = 5.5 V or GND; note 2 3.6
VI = VIH or VIL;
3.6
VO = 5.5 V or GND
VI or VO = 5.5 V
0.0
VCC − 0.5 −
−
V
VCC − 0.2 VCC −
V
VCC − 0.6 −
−
V
VCC − 0.8 −
−
V
−
−
0.40 V
−
−
0.20 V
−
−
0.55 V
−
±0.1 ±5 µA
−
0.1 ±5 µA
−
0.1 ±10 µA
VI = VCC or GND; IO = 0
VI = VCC − 0.6 V; IO = 0
3.6
−
2.7 to 3.6 −
0.1 40 µA
5
500 µA
VI = 0.8 V; notes 3, 4 and 5 3.0
75
−
−
µA
VI = 2.0 V; notes 3, 4 and 5 3.0
−75
−
−
µA
notes 3, 4 and 6
3.6
500
−
−
µA
notes 3, 4 and 6
3.6
−500
−
−
µA
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH32-A) only.
4. For data inputs only; control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input level.
1999 Nov 24
7
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