CY14B104NA-BA25IT Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B104NA-BA25IT Datasheet PDF : 26 Pages
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CY14B104LA, CY14B104NA
Hardware STORE Cycle
Over the Operating Range
Parameter
Description
tDHSB
tPHSB
tSS [45, 46]
HSB to output active time when write latch not set
Hardware STORE pulse width
Soft sequence processing time
20 ns
Min
Max
–
20
15
–
–
100
25 ns
Min
Max
–
25
15
–
–
100
45 ns
Min
Max
Unit
–
25 ns
15
–
ns
–
100 s
Switching Waveforms – Hardware STORE Cycle
Figure 14. Hardware STORE Cycle [47]
Write latch set
HSB (IN)
tPHSB
HSB (OUT)
tDELAY
tSTORE
DQ (Data Out)
tHHHD
tLZHSB
RWI
Write latch not set
tPHSB
HSB (IN)
HSB (OUT)
RWI
tDELAY
tDHSB
tDHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
Figure 15. Soft Sequence Processing [45, 46]
Address
CE
VCC
Soft Sequence
tSS
Command
Address #1
tSA
Address #6
tCW
Soft Sequence
tSS
Command
Address #1
Address #6
tCW
Notes
45. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
46. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
47. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-49918 Rev. *L
Page 16 of 26
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