CXD1196 Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD1196

CD-ROM DECODER

Sony Semiconductor 

CXD1196AR

2.1.10 DMAXFRC-L

2.1.11 DMA Control (DMACTL) register

Bit7 DMAXFRC11

Bit11 (MSB) of DMAXFRC (Transfer Counter)

Bit6 DMAXFRC10

bit10 of DMAXFRC

Bit5 DMAXFRC9

bit9 of DMAXFRC

Bit4 DMAXFRC8

bit8 of DMAXFRC

Bit3 DMAEN (CPU DMA Enable)

‘H’ : To enable DMA

‘L’ : To inhibit DMA

Bit2-0 RESERVED

The DMAXFRC (DMA Transfer Counter) is a counter which indicates the number of DMA transfers. Each

time the data to be transferred to the CPU is read from the buffer, the counter is decremented. When the

value of the DMAXFRC reaches 0, DMA ends. At this point, interrupt request may be output to the CPU.

When data transfer is not to be ended by DMAXFRC as in the case of data transfer in the I/O mode,

DMAXFRC should be set at 0 when data transfer is started (when DMAEN bit is set at ‘H’). The CPU can

read and set the contents of DMAXFRC at any time. During execution of DMA, do not change the contents

of DMAXFRC.

2.1.12 DRVADRC-L (Drive Address Counter-L)

2.1.13 DRVADRC-H

The DRVADRC is a counter which retains the address for writing the data from the drive to the buffer.

When the drive data is written to the buffer, the value of DRVADRC is output from MA01-14 pins. Each

time a byte of data from the drive is written to the buffer, the DRVADRC is incremented.

Before execution of the write only mode and real time correction mode of the DECODER, the CPU sets the

buffer write head address in the DRVADRC.

The CPU can read and set the contents of DRVADRC at any time. During execution of DMA, do not

change the contents of DRVADRC.

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