CXA2006 Просмотр технического описания (PDF) - Sony Semiconductor

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CXA2006

Digital CCD Camera Head Amplifier

Sony Semiconductor 

CXA2006Q

CDS:

The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)

is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output

by the SH2 output, and the signal level is sampled, held and output by the SH3 output.

CDSCLP:

The CDSCLP stabilizes the input signal DC level, clamps (CLPDM) the input signal during the idle transfer

interval for the purpose of eliminating the AGC input offset, and synchronizes the DC level ([∗1], [∗2]) of SH2

and SH3.

AGC:

The gain can be varied from 8 to 38dB by adjusting the AGCCONT voltage control VAGCCONT from 0 to 3V.

LPF:

A primary low-pass filter is installed for the purpose of eliminating unused bands and white noise and

improving S/N.

CAMSH:

The CAMSH is used for camera signal processing system. It is a sample-and-hold circuit which synchronizes

the data read-in timing for the external A/D.

AGCCLP:

The basic black level is set ([∗3]) by clamping the AGC output waveform with the CLPOB clock during the OPB

interval. The AGCCLP capacitance is connected to the AGCCLP pin.

BLK:

The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not

fall below the basic black level and replacing the DC potential. ([∗4])

The signal is blanked when PBLK is low.

C/VSW:

When the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages are set so that the camera signal processing

system operates, C/VSW conducts the BLK output (camera signal) into the DRV. In addition, when these

voltages are set so that the video signal processing system operates, C/VSW conducts the VISH output (video

signal) into the DRV.

OFFSET SW:

The OFFSET SW selects [OFFSET], [CH/CLDC] or [LOUTCLP] as the offset adjustment input pin of the DRV

block and activates these pins by selecting the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages.

When the camera signal processing system is in camera mode, the OFFSET pin is conducted [OFFSET],

allowing the camera signal offset to be adjusted. ([∗5])

When the video signal processing system is in LIN mode, the LOUTCLP pin is conducted [LOUTCLP],

clamping the video composite signal at its sync level and offsetting the signal. In addition, CH/CL mode

conducts the CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band

chroma signals of the video signal.

DRV:

DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW,

and offset adjusted signals are output from DRVOUT pin.

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