CXA1898Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXA1898Q

Recording/Playback Equalizer Amplifier

Sony Semiconductor 

2. 11-bit serial data interface

CLk (Pin 24)

DATA (Pin 25)

LATCH (Pin 23)

XRESET (Pin 26)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

CXA1898Q

• The DATA signal is taken in at the rising edge of the CLK signal.

• The DATA signal is taken in to the internal shift register when the LATCH signal is low.

(Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.)

• The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal.

(Internal shift register data is loaded while the LATCH signal is high.)

• The CLK signal of 11th bit should fall after the LATCH signal rises.

• Reset is done when the XRESET pin is low. (asynchronous method)

Outputs (Pins 13 to 22) are all high (open) during reset.

DATA

(Pin 25)

D1

Control signal

M2

Output pin

Pin 22

Output

Input set at low

L

Input set at high

H (OPEN)

D2

M1

Pin 21

L

H (OPEN)

D3

PL2

Pin 20

L

H (OPEN)

D4

PL1

Pin 19

L

H (OPEN)

D5

BPB

Pin 18

L

H (OPEN)

D6

BPA

Pin 17

L

H (OPEN)

D7

PB-MUTE

Pin 16

L

H (OPEN)

D8

AGC-OFF

—

AGC function stops AGC function operates

D9

SPEED

Pin 15

Low, normal speed

High (open) 1.7

D10

DECK-AB

—

A DECK selected

B DECK selected

D11

REC-MUTE

Pin 14/Pin 13

Low mute OFF

High (open) mute ON

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