CS98100 Просмотр технического описания (PDF) - Cirrus Logic

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CS98100

DVD Processor for Low Cost DVD Players

Cirrus Logic 

CS98100

1.2.4 Digital Video Interface Timing

Figure 7 illustrates the signal timing for the digital video interface pins. The clock is without a polarity to

show the clock may be inverted by register programming. This also illustrates that data is clocked out on

both clock edges in progressive mode. The data order is Cr,Y0,Cb,Y1, and the sync outputs may be pro-

grammed as active high or active low.

Symbol

tvocper1

tcovo12

tcovo22

Description

CLK27_O period

VDAT[7:0] delay from CLK27_O

Vsync/Hsync delay from CLK27_O

Min

-10

-10

Typ Max

37.037

10

10

Unit

ns

ns

ns

Table 4. CS98100 Digital Video Interface Characteristics

1.Values are guaranteed by design only

2.It is recommanded that the output data should be taken at the opposite edge of the CLK27_O.

CLK27_O

(Output)

VDAT[7:0]

(Output)

VSYNC/HSYNC (Output)

Tvocper

Tcovo1

Tcovo2

Figure 7. CS98100 Digital Video Interface Timing Diagram

12

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