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CDB5366(2007) Просмотр технического описания (PDF) - Cirrus Logic

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производитель
CDB5366
(Rev.:2007)
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CDB5366 Datasheet PDF : 41 Pages
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CS5366
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Parameter
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode1
Master Mode
SCLK Frequency
SCLK Period
SCLK Duty Cycle (Note 2)
1/(256*216 kHz)
(CLKMODE = 0)(Note 3)
(CLKMODE = 1)(Note 3)
FS setup
FS setup
FS setup
FS width
before SCLK rising (Single-Speed Mode)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Quad-Speed Mode)
in SCLK cycles
SDOUT setup
SDOUT hold
before SCLK rising
after SCLK rising
Slave Mode
SCLK Frequency (Note 4)
SCLK Period
SCLK Duty Cycle
1/(256*216 kHz)
FS setup
FS setup
FS setup
FS width
before SCLK rising (Single-Speed Mode)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Quad-Speed Mode)
in SCLK cycles
SDOUT setup
SDOUT hold
before SCLK rising
after SCLK rising
Symbol
-
-
-
tPERIOD
tHIGH1
tHIGH1
tSETUP1
tSETUP1
tSETUP1
tHIGH2
tSETUP2
tHOLD2
tPERIOD
tHIGH1
tSETUP1
tSETUP1
tSETUP1
tHIGH2
tSETUP2
tHOLD2
Min
2
54
108
256*Fs
18
40
28
20
18
5
128
5
5
-
18
28
20
20
10
1
5
5
Typ
-
-
-
-
-
50
33
-
-
-
-
-
-
256*Fs
-
-
-
-
-
-
-
-
Max
54
108
216
Unit
kHz
kHz
kHz
256*Fs
Hz
-
ns
60
%
38
%
-
ns
-
ns
-
ns
128
-
-
ns
-
ns
-
Hz
-
ns
65
%
-
ns
-
ns
-
ns
244
-
-
ns
-
ns
Notes:
1. TDM Quad-Speed Mode only specified to operate correctly at VLS 3.14 V.
2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
Clocking” on page 10.
3. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaran-
teed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25.
t PERIOD
t HIGH1
SCLK
FS
SDOUT
data
t SETUP1
t HIGH2
new frame
t SETUP2
data
t HOLD2
Figure 4. TDM Timing
data
16
DS626F2

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