CS43L21-CNZR Просмотр технического описания (PDF) - Cirrus Logic
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CS43L21-CNZR Datasheet PDF : 63 Pages
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CS43L21
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 8)
Frequency Response 10 Hz to 20 kHz
Passband
StopBand
StopBand Attenuation (Note 9)
Group Delay
De-emphasis Error
Min
-0.01
to -0.05 dB corner 0
to -3 dB corner 0
0.5465
50
-
Fs = 32 kHz -
Fs = 44.1 kHz -
Fs = 48 kHz -
Typ
-
-
-
-
-
10.4/Fs
-
-
-
Max Unit
+0.08
dB
0.4780 Fs
0.4996 Fs
-
Fs
-
dB
-
s
+1.5/+0 dB
+0.05/-0.25 dB
-0.2/-0.4 dB
Notes:
8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30
on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
9. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL.)
RESET pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Slave Mode
Input Sample Rate (LRCK)
Parameters
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Symbol
(Note 10)
(Note 11)
Min
1
1.024
45
Quarter-Speed Mode Fs
4
Half-Speed Mode Fs
8
Single-Speed Mode Fs
4
Double-Speed Mode Fs
50
45
1/tP
-
45
ts(LK-SK)
40
ts(SD-SK)
20
th
20
Max
-
38.4
55
Units
ms
MHz
%
12.5
kHz
25
kHz
50
kHz
100
kHz
55
%
64•Fs
Hz
55
%
-
ns
-
ns
-
ns
16
DS723A1
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