C8051F362 Просмотр технического описания (PDF) - Silicon Laboratories
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C8051F362 Datasheet PDF : 288 Pages
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C8051F360/1/2/3/4/5/6/7/8/9
C2CK/RST
VDD
GND
C2D
Reset
Power-On
Reset
Supply
Monitor
Debug / Programming
Hardware
CIP-51 8051
Controller Core
32/16 kB ISP FLASH
Program Memory
256 Byte RAM
1 kB XRAM
2-cycle 16 by 16 Multiply
and Accumulate
XTAL1
XTAL2
System Clock Setup
External
Oscillator
Internal
Oscillator
Clock
Multiplier
Low Frequency Oscillator
Port I/O Configuration
SFR
Bus
Digital Peripherals
UART0
Timers 0, 1,
2, 3
PCA/WDT
Priority
Crossbar
Decoder
SMBus
SPI
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
VREF
VDD
Analog Peripherals
CP0
+
-
10-bit P0.1
CP1
+
IDAC
-
VREF
2 Comparators
10-bit
A
200 ksps
M
ADC
U
X
C8051F361/6/8 only
AIN0–AIN20
VDD
Temp
Sensor
Figure 1.2. C8051F361/4/6/8 Block Diagram
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
C2CK/RST
VDD
GND
C2D
Reset
Power-On
Reset
Supply
Monitor
XTAL1
XTAL2
Debug / Programming
Hardware
CIP-51 8051
Controller Core
32/16 kB ISP FLASH
Program Memory
256 Byte RAM
1 kB XRAM
2-cycle 16 by 16 Multiply
and Accumulate
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0, 1,
2, 3
PCA/WDT
Priority
Crossbar
Decoder
SMBus
SPI
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
System Clock Setup
External
Oscillator
Internal
Oscillator
Clock
Multiplier
Low Frequency Oscillator
VREF
VDD
Analog Peripherals
CP0
+
-
10-bit P0.1
CP1
+
IDAC
-
VREF
2 Comparators
10-bit
A
200 ksps
ADC
M
U
X
C8051F362/7/9 only
AIN0–AIN20
VDD
Temp
Sensor
Figure 1.3. C8051F362/5/7/9 Block Diagram
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Rev. 1.0
21
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